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AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 1 designing dc/dc converters with the si9110 switchmode controller in distributed power systems and battery-powered equipment, the advantages of mos over bipolar technology for pulse- width modulation (pwm) controllers are significant. first, by using a bic/dmos power ic process, a high-voltage dmos transistor can be integrated with a cmos pwm controller to serve as a pre-regulator stage. this reduces the number of external components by permitting the power controller ic to interface directly to the power bus. the second advantage of mos is speed. bipolar pwm controllers can be made fast, but only with a significant increase in supply current. logic gate delays of 5 ns are readily achievable using 5-m cmos, comparator propagation delays are in the 50- to 100-ns range, and the supply current is maintained below 1 m a. how does speed translate into power supply performance? the answer is first in reliability and second in power density. if the delay time is long between the sensing of an overcurrent condition in the power switch and the turn-off of the switch, then the peak and rms current values reach excessive levels and the switch fails. a well-designed power supply should tolerate a continuous short circuit on any output. to accomplish this with a slow controller ic, extra protection circuitry or an oversized switching transistor and heatsink are required. but that costs money. power supply density (often expressed as output power in watts divided by volume in cubic inches) has steadily been increasing over the past 5 to 10 years. by increasing the switching frequency, the size of magnetics and filter capacitors has been reduced, allowing smaller and less expensive power supplies to be built. to increase the switching frequency to the 100- to 500-khz range and still achieve high reliability requires that the current limit delay time be kept under approximately 100 ns. the first bic/dmos switchmode controller ic to meet these requirements is the si9110. its 500-khz rating for maximum switching frequency is fully usable, thanks to the high-speed current limit comparator and the efficient output driver stage, which essentially eliminates the shoot-through current found in bipolar totem-pole circuits. the dmos transistor in the input pre-regulator has a breakdown voltage rating of 120 v, which provides ample headroom for operation from typical bus voltages in distributed power systems (where 12, 24, 48, and 60 v are frequently encountered). the appeal of such distributed power processing systems is in their flexibility and reliability. by bussing power at a higher voltage, smaller conductors can be used, as well as fewer connector pins to get the power to where it is needed-on the circuit card. an on-card power supply can then provide the voltages needed in that part of the system. the power bus voltage is usually chosen to be low enough to eliminate the need for safety agency approvals, and a battery can be connected through a diode to the power bus to provide emergency back-up. the distributed power approach is employed in telecom systems, large minicomputers, and in other applications where reliability is a primary concern. to illustrate some of the performance capabilities of this bic/ dmos switchmode controller ic, a 15-w forward converter design is presented. the converter provides +5-v and 12-v outputs from a 9- to 36-v input range. this permits the power supply to operate from 12-v or 24-v batteries, or from a 28-v aircraft power source. before describing the forward converter example, it is instructive to review the operation of each of the si9110 switchmode controllers functional blocks. functional description pre-regulator a bic/dmos power integrated circuit process is used to integrate a high-voltage (120-v rated) lateral dmos transistor with the cmos pwm controller. by using an ion implant to shift the gate threshold to a negative value, as shown in figure 1, the transistor is made to operate as a depletion- mode device. this eliminates the need for a pull-up voltage above v in to turn the device on, and an amplifier and voltage reference can be used to implement a linear regulator, as shown in figure 2. the cmos circuitry is thus protected from transients which appear on the input power bus. figure 1. depletion-mode mosfet characteristics figure 2. pre-regulator/start-up circuit AN703
AN703 vishay siliconix faxback 408-970-5600, request 70577 2 www.siliconix.com in some applications it is useful to turn off the pre-regulator after start-up. this is easily accomplished by using an auxiliary winding on the transformer to develop a bootstrap supply voltage. after the converter starts, its own output feeds 10 to 12 v to pin 6 (v cc ), and the amplifier pulls the gate of the mosfet to the -v in rail. thus, v gs = -v cc , and the device is turned off. oscillator a ring of inverters and internal mos capacitors forms the oscillator circuit, as shown in figure 3. this circuit requires only a resistor (no external capacitor) to program the frequency. the internal capacitance is charged towards v cc through r osc . when the capacitor voltage reaches v cc /2, the cmos logic threshold, inverter inv1 changes state (from high to low), and the inv2 output goes from a low to a high output. the capacitor, c2, provides positive feedback to ensure stable operation without frequency jitter. it also causes the bump at the end of the ramp until inv2 can turn on the discharge switch, q1, to terminate the cycle. oscillator synchronization is achieved by prematurely terminating each clock cycle using a positive going pulse capacitively coupled onto the oscillator ramp voltage. the pulse forces inv1 to change states, q1 discharges c = c1 + c2, and the cycle repeats. an internal flip-flop blanks out the output during every other clock cycle, so the switch duty ratio is limited to a maximum of 50%. therefore, the oscillator frequency and sync pulse repetition rate must be set at two times the switching frequency, f s . error amplifier the bias resistor connected from pin 1 (bias) to pin 5 (-v in ) programs the current sources in the analog portion of the current-mode controller - including the error amplifier, the current-mode and current-limit comparators, and the voltage reference. the si9110 data sheet guarantees the performance of these functions at one value of bias current - 15 a. it is possible to change the performance characteristics of these functions by changing the bias current, and appendix a explains how this is accomplished. the error amplifier circuit employs pmos transistors in a differential input stage to achieve a high input impedance of 40 m w typically (2 m w minimum). this input impedance, combined with a 1-k w small-signal output impedance, enables the amplifier to be used with feedback compensation, unlike transconductance error amplifiers. the amplifier can source 2 ma and sink 0.140 ma, as can be seen from the output stage equivalent circuit in figure 4. yes, an npn transistor is used here. most of the pwm controller is cmos, but the process allows the flexibility of using bipolar devices where they are advantageous. the error amplifier is unity gain stable with a typical bandwidth of 1 mhz and 60 phase margin. bias current values of from 5 a to 50 a have been tested, and the error amplifier does remain stable over this range. actually, the bandwidth and phase margin increase somewhat as i bias is increased above 15 a. higher bias currents may, therefore, be useful when compensating higher frequency converters (above 250 khz). figure 3. si9110 oscillator circuit operation
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 3 figure 4. error amplifier output stage figure 5. current-limit comparator delay (equivalent circuit model) voltage reference a buried zener with merged temperature compensating diode (patent pending) is used to achieve stability of 0.25 mv/ c. the si9110 voltage reference is trimmed to 4 v plus or minus 1% with a bias current of 15 a. this voltage varies by about 1% as i bias is varied from 5 to 50 a. if 1% reference accuracy must be guaranteed, i bias should be set at 15 a. for circuits employing an external reference on the secondary side, such as those used with optically coupled feedback, the si9111 is an economical approach. its voltage reference provides a dc bias point at the input to the error amplifier where its 10% accuracy is more than sufficient. the reference accuracy is the only difference between the si9110 and si9111. comparators the delay time of the current-limit and current-mode comparators can be modeled as a current source charging an internal nodal capacitance, as shown in figure 5. the current- mode comparator is intentionally made to be four times slower than the current-limit comparator. in many circuits, this permits the elimination of the rc filter in the current-sense circuit, which is used to prevent false trips by the leading edge current spike. after one of the comparator outputs goes high, there is an additional 20 ns of gate propagation delay before the output driver can begin switching. the total current-limit delay to output versus i bias is shown in figure 6 for v cc equal to 8.5 v. the delay time is 180 ns for i bias = 5 a, but decreases to 50 ns for i bias = 30 a. as operating frequency is increased, i bias may be increased to speed up the current limiting and reduce the minimum mosfet pulse width. as i bias is increased, however, the current-limit trip voltage also increases. figure 7 shows how the trip voltage is established and how it varies with i bias . the current sense resistor and i bias determine the peak value of switch current. since this current limiting is very fast, the trip level of current is usually set to be well above the maximum normal operating current (by a factor of 1.5 to 2). this prevents false trips but still protects the mosfet switch from exceeding its pulse current ratings. mosfet driver the driver circuit is a cmos inverter whose typical characteristics are shown in figure 8. the n-channel (turn-off) peak drive current is about 20% higher than that of the p-channel (turn-on) device. although the on-resistance (r ds(on) ) of the output drive is specified, usually the saturation current (where d i d / d v ds is very small) determines the switching speed. this is due to the vertical load line of capacitive loads. in other words, the mosfet gate capacitance appears as a short circuit across the drivers output. the cmos driver is fast enough to effectively eliminate cross- conduction current during switching transitions, at least when v cc 10 v. above this level, a small amount of cross conduction occurs. therefore, the greatest gate drive efficiency (approaching 100%) is achieved by keeping v cc 10 v, and the gate drive power is given by p gate = q g x f s x v cc (1) where q g = mosfet gate charge f s = switching frequency v cc = supply voltage
AN703 vishay siliconix faxback 408-970-5600, request 70577 4 www.siliconix.com shutdown logic the shutdown logic employs an rs flip-flop to disable the output drive. both the shutdown and reset inputs have internal current-source pull-ups (equal to i bias ), so they can be left open when unused. as long as the shutdown input is held low, the output is off. if the reset input is hard wired to -v in (through a normally closed reset button if desired), any low input to shutdown will latch the output in the off state. it will remain off until power is recycled (or the reset button is pushed). undervoltage lockout during start-up, the depletion transistor charges the capacitance connected to the v cc pin with a typical charging current of 18 ma. the output is disabled until v cc reaches the uv lockout voltage (typically 8.1 v). the ic requires less than 0.5 ma of current during this time, since the largest component of supply current is usually for the gate drive (see appendix b). when v cc reaches 8.1 v, the output is enabled and the mosfet begins switching. the supply current increases by q g x f s , and v cc charges more slowly until it reaches the pre-regulator voltage (8.5 v). if too much current is drawn from v cc , for instance to supply other circuitry, it may be possible that the converter will be prevented from starting. or it may oscillate on and off as it starts up, loads down the v cc pin, shuts off, and then repeats this cycle. figure 6. current-limit comparator delay vs. bias current figure 7. current-limit trip voltage vs. programmed bias current
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 5 figure 8. output drive characteristics forward converter specifications input voltage: 9 to 36 v efficiency: v in = 12 v, full load: 78% typical, 76% minimum v in = 12 v, ? load: 82% typical, 80% minimum switching frequency 100 khz circuit description the forward converter schematic is shown in figure 9, and a block diagram of the si9110/si9111 controller ic appears in figure 10 for easy reference. the circuit employs a tl431c voltage reference/amplifier to drive the led of the opto- isolator, u3. this maintains galvanic isolation between input and output voltages. since a reference is needed on the secondary side, external to the pwm controller ic, it is not necessary to have a precision reference on the primary side. the voltage reference of the si9111 is specified at 4 v 10%, which is accurate enough to establish a dc bias point for the collector current of u3. if galvanic isolation is not required, then the feedback circuitry in the box can be replaced by a voltage divider network, and the input and output grounds must be tied together. in this configuration, the reference accuracy of the pwm controller ic limits the accuracy of the output voltages, and the si9110 with its 1% reference should be specified. the two ics are identical in all other respects. the smp25n06 switching transistor (q1) is a 25-a, 60-v mosfet in a t0-220 package. the breadboard was operated without a heatsink on q1, even with the power supply output shorted. three secondaries on the transformer, t1, provide isolated voltages of +5 v and 12 v. the output inductors are wound on a common core. this reduces the size and cost compared to separate output chokes, as well as improves the response to dynamic loads. the same core size is used for the transformer and the output inductor, the only difference being the air gap required by the inductor to sustain a dc flux. the transformer does not require a gap since the winding, n2, resets the core flux to zero during the off time of q1. output voltages minimum load (ma) maximum load (a) regulation (%) ripple (mv p-p ) +5 50 1.5 2 150 +12 50 0.310 5 40 -12 20 0.310 5 40
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 6 figure 9. multiple output forward converter
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 7 figure 10. si9110/si9111 block diagram forward converter principle the operating principle of forward converters is illustrated in figure 11. when the switch, q1, is on, the input voltage is applied across the primary winding, n p . if, for example, the input voltage minus the voltage drop across q1 and r2 is equal to 9 v, then 1 v per turn is applied across the primary. since the same magnetic flux links all of the windings, the volts/turn is constant by faradays law [v = -n(d f /dt)]. therefore, v s1 equals 13 v, and v s2 and v s3 equal 30 v. the lc filter has a cut-off frequency well below the switching frequency, so that the average value of the pulsed secondary voltage appears at the output. for v 1 to equal 5 v, the duty ratio, neglecting diode drops, is given by figure 11. forward converter operating principle d v 1 v s1 --------- - 5v 13 v ------------ - 0.385 == = (2)
AN703 vishay siliconix faxback 408-970-5600, request 70577 8 www.siliconix.com the control loop will force the duty ratio to the value required to make the regulated output equal to 5 v. if the duty ratio equals 0.385, the secondary voltages v 2 and v 3 are given by this is the ideal case. the diode drops cause the duty ratio to be higher, and v 2 and v 3 are very close to 12 v. (the measured value was 12.1 v.) when q1 turns off, the free- wheeling diodes cr3, cr5, and cr7 carry the inductor currents. again, if diode drops are neglected, each output voltage appears across its corresponding inductor winding. since the volts per turn must be constant on each winding of l2, the number of turns must be proportional to the output voltage. therefore, the number of turns and the inductance of each winding cannot be arbitrarily assigned as they can be for individual output chokes. the ratio of turns on l2 must be an integer multiple of the t1 secondary windings. in this case, the integer is 1. the amount of inductance is then determined by the core gap, specified as inductance per 1000 turns; 250 mh per 1000 turns was used, giving an inductance for the 5-v inductor as determined from therefore, the current slope during the on time of q1 (referred to the primary side of t1) is given by this current ramp is sensed by r2 to give a voltage ramp input to pin 3 of the si9111. the current-mode comparator changes states and turns the mosfet switch off when this sense voltage exceeds the control voltage, v c , from the output of the error amplifier. thus, the peak inductor current is controlled on a cycle-by-cycle basis. the same current sense signal is also compared to an internally-generated reference of 1.2 v by the current-limit comparator. this comparator is made four times faster than the current-mode comparator to minimize the delay time required to turn the mosfet off when an overcurrent condition exists. such dual-threshold current sensing enables power supply designs that can tolerate shorted outputs for an indefinite period. if the short is removed, then the converter returns to normal operation. measured circuit performance figure 12 shows how the power supply efficiency varies with load. under the low-line condition (v in = 9 v), the full load efficiency is 77%. at higher input voltages, the conduction losses in the mosfet and sense resistor are reduced, permitting full-load efficiency to exceed 80%. high efficiency at light loads is permitted by the cmos controllers low supply current. at v in = 9 v, only 2.3 ma 9 v = 20.7 mw are required by the si9111. the circuit operation at v in = 18 v with a 80% load is illustrated by the waveforms in figure 13. the control voltage out of pin 13 is ac-coupled and shown above the current sense voltage. the downward slope of v c is due to the slope compensation resistor connected between pin 8 and pin 14. slope compensation is explained below in the section on loop analysis and in references 1 and 2. when the +5-v output is shorted to ground, the waveforms appear as in figure 14. the error amplifier output, v c , goes to the positive rail, so the current-mode comparator would allow the duty ratio to increase to 50%. however, the faster current- limit comparator trips at about 9 a, and the duty ratio is limited to less than 10%. figure 12. percent efficiency vs. load current v 2 v 3 v s2 d 30 () 0.385 () 11.5 v == = = (3) l 5v 250 mh 13 1000 ------------ - ? ?? 2 42 m h == (4) di dt ----- 13 9 ------ ? ?? 13 v 5 v C 42 m h ---------------------------- ? ?? 0.275 a m s == (5)
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 9 figure 13. forward converter waveforms figure 14. forward converter waveforms with +5v output shorted to gnd (v in = 18 v) figure 15. power converter with current-mode control control loop analysis current-mode control current-mode control of switching power converters offers several advantages over voltage-mode control. the reliability improvement offered by fast cycle-by-cycle current limiting was discussed above. a second major advantage of current programming is improved dynamic response of the regulator loop while at the same time requiring simpler error amplifier compensation. the basic objective of current-mode control is to make the power stage behave as a voltage-to-current converter (transconductance amplifier), as shown in figure 15. to regulate the output voltage, a feedback loop is employed. the control voltage, v c , is generated by an error amplifier which compares the output voltage to a precision reference, just as in voltage-mode control. there are several methods for implementing the transconductance power amplifier function-all of them employ an inner current feedback control loop. the most common method uses a constant frequency clock and peak current sensing, as shown in figure 16. a clock pulse initiates turn-on of the mosfet switch, and current ramps up in the output inductor. this current, reflected through the transformer turns ratio, is sensed by the resistor in the mosfet source to produce a voltage analog of the inductor current. when the voltage ramp reaches the control voltage, v c , the current-mode comparator sets the latch and turns off the switch. in this way the inner current control loop programs the inductor current in proportion to the control voltage. v ds (20 v/div) v c (pin 13) (500 mv/div) v sense (500 mv/div) (5 a/div) loads: 1.2 a @ +5 v 0.25 a @ 12 v v in = 18 v v ds (20 v/div) v c (pin 13) (500 mv/div) i d (5 a/div)
AN703 vishay siliconix faxback 408-970-5600, request 70577 10 www.siliconix.com to achieve the same loop bandwidth as a current- programmed power converter, a voltage-mode pwm converter requires an error amplifier with compensation as shown in figure 17. figure 16. voltage-to-current converter current-mode control requires fewer compensation components, as shown in figure 18, and the error amplifier has a simpler transfer function. the simplified compensation is due to the elimination of the double pole of the output lc filter, which must be compensated by the double zero at f 1 . if the inner current-programmed loop were perfect, then the inductor would behave as a controlled current source, and the power stage would be a single-pole system. this doesnt happen. what does occur is a splitting of the two poles. one is shifted down in frequency to approximately f p1 = ? p r l c, which is the dominant low-frequency pole. the second pole in the voltage regulator loop occurs at the unity gain crossover frequency, w c /2 p , of the inner current-control loop. the inner current-control loop has less gain than the voltage loop but has more bandwidth. [1] the wide bandwidth of the current loop enables the power converter to respond more rapidly to step changes in load current, even if the small-signal loop bandwidth is the same. it must be realized that step load changes are large signal perturbations between two different small-signal operating points. with inductor current as a controlled parameter, the wideband current loop changes more rapidly between two operating points of load current. the measured response to a step change in load is given in figure 19. the switch current and output voltage recover to steady-state within about 50 s, or five switching cycles. voltage-mode control generally yields a response which is slower by a factor of 5 to 10. figure 17. error amplifier compensation for maximum bandwidth using voltage-mode control figure 18. error amplifier compensation for maximum bandwidth using current-mode control
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 11 figure 19. step load response small-signal analysis a very concise presentation of small-signal analysis of current-mode control loops can be found in reference 1. in that paper, the y-parameter model, shown here in figure 20, is developed for current-programmed power stages since y- parameters give an output current for a unit of control voltage input. the inner current loop is demonstrated to be stable, as long as slope compensation is employed for d > 0.5, and therefore, the current loop can be absorbed into the new power stage model. this has the advantage of allowing us to analyze the stability of only one (voltage) control loop. the derivations will not be presented here, but the resulting control-to-output voltage transfer function of the buck regulator is shown in figure 21. r 22 is the low frequency value of the inverse of the output admittance, y 22 . it is a measure of how effectively current programming makes the power stage behave as a current source and, consequently, depends heavily upon the gain of the inner current loop. more inductance yields higher current loop gain and larger r 22 . smaller r 22 causes the low frequency gain to be diminished, since r 22 appears in parallel with the load, r l . r 22 also decreases the low-frequency pole by the same factor. in this case, r 2c is simply the sense resistance value of 0.1 w . for buck-derived converters, it is the ratio of voltage at the current-mode comparator input to inductor current, and it accounts for current amplifier gains and current transformer ratios. the second pole at w c /2 p depends upon the switching frequency, the amount of slope compensation, and the duty ratio at the dc operating point (remember that this is a small- signal analysis of variations around a dc operating point); it does not depend on the load current. an easy way to work through the calculations is to form a table, as shown in table 1. the voltage-control loop bandwidth, f vc , and phase margin, f m , are calculated at full load for three different input voltages. the same symbols are used as in reference 1, with the exceptions that the current ramp slopes m 1 , m 2 , and m 3 are referenced to the current- mode comparator input. the result is the same as long as the current scale factor, r f , is taken into account. figure 20. y-parameter model for current-mode regulators figure 21. small-signal control to output transfer function of current-programmed buck regulators +5 v (500 mv/div) i d (5 a/div) v gs (10 v/div)
AN703 vishay siliconix faxback 408-970-5600, request 70577 12 www.siliconix.com table 1. 15-w forward-converter stability analysis figure 22. implementation of slope compensation using the si9110 the forward converter is a transformer-isolated derivative of a buck regulator. therefore, the y-parameter model for the buck regulator applies here, but the r, l, and c values used must be reflected through the transformer turns ratios. the resulting circuit parameters are slope compensation is achieved by feeding the oscillator ramp voltage into the inverting input of the error amplifier, as shown in figure 22. the amount of slope compensation is given by this calculation does not take into account the effect of ripple feedback upon slope compensation. for a buck regulator, during the on time of the switch, the output ripple voltage is ramping upward due to capacitor esr. this ramp voltage is amplified and inverted by the error amplifier to provide additional slope compensation. if lower esr capacitors are used, this effect is diminished. for film or ceramic filter capacitors, the ripple is also phase shifted, since ripple voltage is determined more by c than by esr. the slope compensation parameter, n, is given by where m 1 is the current ramp slope (times the sense resistance) during t on , which is calculated from v in d i m 1 (v/s) n r 2c r 22 f p * (hz) a cm = w c (krad/s) f vc (khz) f m (deg) 9 0.59 0.044 1.6 0.1 7.6 144 7.5 (17.5db) 2 p (33.7) 15.76 52 18 0.78 0.089 1.3 0.1 5.1 147 7.2 (17db) 2 p (31.4) 15.77 50 32 0.88 0.158 1.16 0.1 4.5 152 7.0 (17db) 2p (31.2) 15.85 50 * f p 1 2 p r 22 r l || () c -------------------------------------- - = r 5v 1.5 a -------------- 9 13 ------ ? ?? 2 12 v 0.31 a ----------------- - 9 30 ------ ? ?? 2 12 v 0.31 a ----------------- - 9 30 ------ ? ?? 2 1.6 w 3.5 w 3.5 w 0.83 w = == (6) la l n 2 1000 ------------ - ? ?? 2 n 1 n 2 ------ - ? ?? 2 20.3 m h == (7) c 220 m f 13 9 ------ ? ?? 2 47 m f47 m f + () 30 9 ------ ? ?? 2 + 1500 m f == (8) m c v cc t s ---------- - r fb r slope -------------------- 8.5 v 10 m s --------------- 150 k w 108 m w --------------------- - 0.071 v m s == = (9) n1 2m c m 1 ------------- - + = (10) m 1 v in l -------- - r f v in 20.3 m h --------------------- - 0.1 w == (11) r 22 || r l r 2c
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 13 for a buck converter, r 2c is simply equal to r f , the sense resistance. the conduction parameter k is a measure of how far into continuous conduction the converter is operating. at full load this converter operates heavily into the continuous conduction mode and has a fairly high current-loop gain. the output resistance parameter is which varies with both input voltage and load. the frequency, f p , of the power stage low-frequency pole is the low-frequency gain of the power stage is and the high-frequency pole is given by w c = w s / p nd . once the gain of the power stage has been determined and plotted, as shown in figure 23, the objective is to establish values for the error amplifier compensation to provide good loop bandwidth and phase margin. some typical rule-of- thumb numbers are to use a bandwidth of one sixth to one fifth of the switching frequency and a phase margin of 45 to 60 . a series rc network in the feedback of the error amp gives a pole at the origin and a zero at f z = ? p r fb c fb . figure 23. bode plot of small-signal loop gain the error amplifier gain remains constant at between f z and the point where the open-loop gain of the error amplifier takes over. this occurs at a ol1 = bw/a 1m , where bw is the error amplifier bandwidth. the gain of the loop is decreased to unity below the poles at w c /2 p , and a ol1 , but each can contribute significant phase shift. the voltage loop crossover frequency is calculated from f vc = a cm x a 1m x f p (16) the feedback divider resistor, r 7 , was first arbitrarily chosen to be 10 k w . (this is for the non-isolated configuration. for analysis of the optical-isolator circuit, see appendix c.) to achieve f vc @ f s /6 = 16 khz, a 1m was calculated from equation 15. this requires r fb = a 1m x r div = 15 x 10 k w = 150 k w a standard capacitance value is then chosen such that f z falls somewhat below f p . c fb = 0.018 f places the zero, f z , at about 60 hz. the phase margin, f m , of the ideal current-mode converter is 90 . phase lags due to poles at w c /2 p and a ol1 diminish the phase margin according to a more accurate analysis should account for the zero of the capacitor esr. the tantalum capacitors used here (type 550d from sprague) will cause a zero at approximately 30 to 50 khz. this will just about cancel the pole at w c /2 p , and increase the phase margin. higher esr will cause the extra zero to fall below f vc , and the loop bandwidth will be increased somewhat. magnetics design transformer core selection the core selection method used here employs the core geometry parameter, k g , as proposed by mclyman. [3] pot cores were chosen for both the transformer and the coupled inductor, but another design approach using toroids is recommended for applications requiring either the lower profile or the resilience to thermal shock that toroids provide. begin by calculating the output power of the transformer. p o = s (v o + v d ) i o (18) where v o o output voltage v d o diode drop i o o output current k 2l rt s ----------- 2 20.3 m h () 0.83 () 10 m s () ------------------------------------- 1.86 == = (12) r 22 kr nd d C ------------------- - = (13) f p 1 2 p r 22 r || l () c -------------------------------------- - = (14) a cm r 22 r || l () r 2c = a 1m r fb r div ---------- - r 4 r 7 ------ - 150 k w 10 k w ------------------- - 15 or 23.5 db () === = (15) f m 90 deg tan 1 C f vc w c 2 p ------- ------- - ? ? ? ? ?? tan 1 C f vc a ol1 ------------ - ? ?? C C @ (17)
AN703 vishay siliconix faxback 408-970-5600, request 70577 14 www.siliconix.com p o = (5 v + 0.5 v)(1.5 a) + 2(12 v + 0.7 v)(0.31 a) = 16.1 w (19) the apparent power, p t , for a single-ended forward converter is where h transformer efficiency the electrical conditions parameter, k e , is given by k e = 0.145 k e 2 f 2 b m 2 x 10 -4 (22) where k f o waveform factor ( for the forward converter) f o operating frequency b m o maximum flux density (0.15 tesla was chosen) finally, the core geometry, k g , is where a o percent regulation (use 1%) this k g calculation is based upon an assumed window utilization factor, k u , of 40% or 0.4. this is difficult to achieve using small pot cores. assuming a 25% window area, the core geometry is adjusted by k g(new) = (0.4/0.25) (3.5 x 10 -3 ) = 5.6 x 10 -3 cm 5 (26) the closest pot core is number 1811pl00 from ferroxcube, for which k g = 6.0 x 10 -3 cm 5 . the toroidal cores which most nearly meet the transformer requirements are numbers t8-16-8 and t10-20-5 from tdk. their k g s are 0.007456 cm 5 and 0.007536 cm 5 , respectively. transformer winding design (first iteration) refer to figure 11 for the nomenclature used here. the number of primary turns is calculated from faradays law, which states that v = -n(d f /dt). where a c o cross-sectional area of core b max o maximum flux density t on o mosfet on-time (t on = d x t s ) design for d max = 0.475 at v in = 9 v. v p is calculated from v p = v in - i d x (r ds(on) + r sense ) (29) and calculate the secondary turns as follows: v o = [(v p ) (n s /n p ) - v d ] x d (33) if v o = v 1 = 5 v, d = 0.475, and v p = 8.2 v, then n s1 = 8.07. (assume the diode drop is 0.5 v for schottky diodes and 0.7 v for fast recovery p-n diodes.) eight turns is close enough. now find the number of turns for the 12-v secondary. during the off-time, the output voltages appear across each coupled inductor winding, which must have the same turns ratios as the transformer secondaries. therefore, p t p o 2 h --- 2 + ? ?? = (20) p t 16.1 () 2 0.99 ----------- 2 + ? ?? 45.8 va = = (21) 2 k e 9.145 2 () 2 10 5 () 2 0.15 () 2 10 4 C 6525 == (23) k g p t 2k e a ---------------- = (24) k g 45.8 2 6525 () 1 () ------------------------------ 3.5 10 3 C cm 5 == (25) v p n p ------ - a c b max t on ------------ - = (27) n p v p t on b max a c -------------------------- - = (28) i d p o h ------- ? ?? v in d ------------------- @ 15 w 0.8 -------------- ? ?? 9v () 0.475 () ---------------------------------- 4.4 a == (30) v p 94.4 C 0.08 0.10 + () 8.2 v == (31) n p 8.2 v () 4.75 m s () 0.15 t () 0.433 10 4 C m 2 () -------------------------------------------------------------------- - 6 turns == (32) 5v 0.5v + n s1 ------------------------------ 12 v 0.7 v + n s2 --------------------------------- - = (34)
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 15 n s1 = 8 gives n s2 = 18.5 turns; 18 turns give v 2 @ 11.65 v, and 19 turns give v 2 @ 12.35 v. another option is to set n s1 = 16 and n s2 = 37. this will more closely achieve the desired turns ratios, but copper losses will be greatly increased. remember that if the number of turns is doubled, then the copper cross section must be halved. resistance, and copper losses, increase by a factor of four. if it doesnt matter that the 12-v output is off a bit, then use n p = 6, n s1 = 8, and n s2 = 19. inductor core selection the power handling capability of the core is independent of the number of windings used. the simplest approach is to refer all outputs to the 5-v winding and assume that i o = p o /v o = 15 w/5 v = 3 a (35) to operate well into continuous conduction choose k = 2l/ rt s 3 4. therefore, l 3 (4/2)(5 v/3 a)10 -5 =33h. this is a ball park number; 25 h is acceptable, and so is 50 h. however, if l is larger, a larger core is required for the same core losses. the peak inductor current, at maximum load, is d i is approximately given by and the maximum d i occurs at maximum v in where d @ 0.11, t off = (1 - d)10 s = 8.9 s. the inductor energy storage requirement is e = ? (li 2 ) = ? (33 m h)(3.75) 2 = 232 m j (40) the electrical conditions are k e = 0.145 (p o ) (b m ) 2 10 -4 (41) = 0.145 (15) (0.3) 2 10 -4 = 19.6 x 10 -6 the core geometry requirement is for 1% regulation. adjust this for a 25% window utilization, and you get we can use an 1811 pot core with a standard a l value (160, 250, or 400 mh/10 3 ). for a toroid, use a number 55206 molypermalloy powder core, for which k g = 0.007274 cm 5 . the pot core was chosen here. inductor winding design the transformer design was left with n s1 = 8 and n s2 = 19, which causes the 12-v output to be about 12.35 v. if a l = 400 mh/1000 turns is used, l s1 = (8/1000) 2 (0.4) = 25.6 m h (44) this gives which is still well into continuous conduction (k crit = d = 1 - d for buck converters). it could be done this way, but to make the 12-v output come out closer to 12 v, try some other turns ratios. n s1 = 13 and n s2 = 30 gives: v 2 = (5.5/13)30 - 0.7 = 11.99 v (46) a l = 250 mh/1000 turns gives l s1 = (13/1000) 2 (0.25) = 42 m h (47) the maximum flux density is found from saturation occurs above 0.3 t = 3000 gauss, so this flux level is acceptable. apportion the window area according to the output power of each winding. total copper area is 0.25 w a , where w a = 0.285 cm 2 is the total window area. the copper cross section for the 5-v winding is ii omax () di 2 ------ + = (36) v 1 v d + l s1 -------------------- i d t off ----------- = (37) 5v 0.5v + 33 m h ------------------------------ i d 8.9 m s ----------------- = (38) k g e () 2 k e a ----------- 232 m j () 2 19.6 10 6 C () 1 () ------------------------------------------ - 0.00275 cm 5 == = (42) k g 0.4 0.25 ----------- 0.00275 () 4.4 10 3 C cm 5 == (43) k 2l rt s ----------- 2 25.6 m h () 1.67 () 10 5 C () --------------------------------- 3.1 == = (45) l l i -- - n f i ------- nb m a c i -------------------- == = (48) bm li na c ----------- - 42 m h () 3.75 a () 13 () 0.433 10 4 C () ------------------------------------------------- - 0.28 t == = (49) a cu 0.25 () 0.285cm 2 () 30 turns ------------------------------------------------ 5v () 1.5 a () 15 w --------------------------------- 2.74 10 3 C cm 2 == (50)
AN703 vishay siliconix faxback 408-970-5600, request 70577 16 www.siliconix.com use two strands of awg26 magnet wire, for which the copper area is a w = (2) (1.28 x 10 -3 cm 2 ) = (2.56 x 10 -3 cm 2 ) (51) for the 12-v winding, use one strand of awg30, for which a w = 0.507 x 10 -3 cm 2 . transformer winding design (revisited) as shown in the above analysis, the transformer and inductor designs are interdependent when coupled inductors are used. calculations are made based upon some reasonable assumptions, and the results may not give the desired outcome (such as a fractional turn or a saturated core). then choices must be made which are consistent with the requirements of the end application. the choice made here was to set the output voltages as close as possible to 5 and 12 v. the transformer secondary turns are n s1 = 13 and n s2 = 30. the primary turns are found from v s = v o /d + v d = v p (n s /n p ) (53) set n p = 9 turns so that the converter will continue to regulate down to v in = 9 v. again, apportioning the copper according to power level (and equally split between primary and secondary) gives the following winding configuration. winding tu r n s wire size the primary and reset windings were wound together (multifilar) over the bobbin, followed by the 5-v output. the 12-v windings were wound bifilar over the 5-v winding. prototyping hints a schematic and a parts list do not provide sufficient information to enable a cad operator to lay out a switching power supply. parasitic inductances and capacitances, which do not appear on the schematic, can cause major differences in performance. the number of layout iterations can be reduced (down to one with experience) if the following guidelines are followed. 1. use a ground plane. however, do not assume that the ground plane impedance is zero so that you can ignore the need for good component placement. every component cannot be placed near every other component. know which components should be grouped closely together and when close proximity is unnecessary. 2. keep loop areas small where the current changes rapidly. loop inductance is proportional to loop area. inductive voltage spikes are proportional to inductance, i.e, v = ldi/ dt. for example, the loop from c1, through the t1 primary, q1, r2, and back to the bottom end of c1 carries a current which undergoes a high rate of change. reducing this loop area reduces noise on the input power lines. other examples are the loops defined by each secondary winding and the corresponding output rectifiers. cross regulation of the 12-v outputs is worsened by the inductance of these loops. conversely, the inductance of the loop defined by cr3, l2, and c7 is not critical. the parasitic inductance in series with an inductor is of little consequence. 3. keep noise-sensitive nodes away from noise generators. the drain voltage of q1 changes rapidly. if the trace between t1 (primary) and q1 (drain) runs adjacent to the feedback input (pin 14) of u1, then noise is capacitively coupled into the feedback. the noise current is proportional to the parasitic capacitance by i = cdv/dt. injected noise currents are worse when the driving point impedance is high. pins 1, 13, and 14 of the switchmode controller are such high-impedance nodes. too much noise injection causes a random instability in the control loop. following these guidelines reduces headaches as well as costly design time. using bic/dmos pwm controllers reduces component count and failure rates of dc/dc converters in distributed power systems. references 1. middlebrook, r.d., topics in multiple-loop regulators and current-mode programming, ieee power electronics specialists conference, 985 record, pp. 716-732 (ieee publication 85ch2117-0). 2. hsu, et al., modelling and analysis of switching dc-to-dc converters in constant-frequency current-programmed mode, ieee power electronics specialist conference, 1979 record, pp. 284-301, (ieee publication 79ch1461-3 aes). 3. mclyman, col. w. t., magnetic core selection for transformers and inductors, marcel dekker,1982. primary 9 3 strands awg26 reset 9 1 strand awg32 + 5 v 13 1 strand awg26 +12 v 30 1 strand awg32 -12 v 30 1 strand awg32 a cu 0.25 () 0.285cm 2 () 30 turns ------------------------------------------------ 12 v () 0.31 a () 15 w ---------------------------------------- - 0.59 10 3 C cm 2 == (52) v s 5v 0.475 -------------- - 0.5 + 11 v 8.2 v 13 n p ------ - ? ?? === (54) n p 9.67 turns =
AN703 vishay siliconix faxback 408-970-5600, request 70577 www.siliconix.com 17 appendix a proper operation of the si9110 requires that a programming resistor, r bias , be connected from pin 1 to -v in , which is assumed here to be ground. this resistor programs internal current sources in the analog portion of the control circuitry. the value of the bias current depends upon two parameters, v cc and r bias , as shown in the circuit provided in figure 24. the characteristic curve of the pmos fet follows the familiar square law (i d is proportional to v gs squared). however, over the region of interest, between 5 a and 50 a, the curve can closely be approximated by a straight line, as shown in figure 25. this line is defined by its slope (50 k w ) and its point of intersection with the x-axis (3.5 v). the intersection of this curve with the load line defined by v cc and r bias determines the value of i bias . the load line in figure 25 identifies the conditions which are specified in the data sheet. when v cc = 10 v and r bias = 390 k w , i bias = 15 a. if the pre-regulator is used continuously, as in the forward converter example above, then v cc has a nominal value of 8.5 v. the 1-m w bias resistor gives i bias = 5 a. this is the lowest value recommended. on the high end, not much performance improvement in terms of comparator speed is obtained for i bias above 30 a (see figure 6). figure 24. internal current source programming figure 25. programmable current regulator characteristics
AN703 vishay siliconix faxback 408-970-5600, request 70577 18 www.siliconix.com appendix b the supply current requirements of pwm controller ics are specified at one operating frequency, with no load being driven. in many cases, it may be useful for the circuit designer to determine the supply current requirements needed to drive a specific mosfet at a given frequency. the si9110 has been well characterized in this regard. equation 1 provides a quick calculation of the supply current drawn by the si9110. each of the components has a straightforward explanation. a. the voltage reference requires a constant current which is neither frequency nor load dependent. it has a typical value of 60 a. b. cmos circuitry only uses power when a change in logic state occurs. therefore, the quiescent current requirements of the oscillator and logic gates is proportional to the switching frequency. the proportionality constant is typically 1.5 a per khz. c. the analog circuitry (error amplifier and comparators) utilizes constant-current sources which are programmed by the bias resistor connected from pin 1 to ground. setting r bias equal to 390 k w and v cc = 10 v programs the bias current at 15 a. at this current, the internally generated voltage reference levels (for undervoltage lockout, v ref , and v cl ) have the best compensation over temperature. this is also the value at which the data sheet parameters are guaranteed. d. the output drive current is typically the largest component of i cc . the drive stage has been designed to minimize shoot-through current of the output inverter. thus, the current requirement can be calculated as i gate = c l v cc f s . a mosfet gate is a capacitive load, but a non-linear one. therefore, mosfet manufacturers specify the total gate charge required to turn a mosfet on. in this case, i cc = q g(on) x f s , where fs is the switching frequency. for the forward converter example, the supply current should be voltage reference = 60 a oscillator and logic = (1.5 a)/khz x 100 khz = 150 a analog circuitry = 30 x 5 a = 150 a gate drive 15 nc x 100 khz = 1500 a total supply current = 1860 a the measured value was 2.1 ma. appendix c the gain of the error amplifier plus the feedback isolation circuit is which is approximately equal to the gain of the non-isolated feedback circuit analyzed above. the tl431c has a voltage reference with 2% accuracy equal to 2.5 v. r 7 and r 8 were both chosen to be 1 k w to establish a dc current much greater than the input bias current of u2, which is 4 a. c 10 causes the amplifier of u2 to behave as an integrator with a high dc gain, thus ensuring the accuracy of the output voltage. r 9 causes the gain of u2 to remain constant at r 9 /r 7 above the crossover frequency, 1/ (2 p r 9 c 10 ). the minimum current transfer ratio (ctr) of u3 is 0.07. ctr is defined as the ratio of output current to anode current for the optical isolator. the small-signal variation of the led current is equal to the output voltage of u2 divided by r 10 . the output voltage of u3 is equal to the output current of u3 times r 11 . therefore, the gain from the output of u2 to the output of u3 is given by ctr(r 11 /r 10 ). r 11 was chosen to establish a dc operating current for u3 given approximately by likewise, r 10 establishes the dc operating point for the led at approximately 1 ma. r 9 and r 12 are chosen last to achieve the desired overall gain. i cc 60 m a1.5 m a f s 1000 ------------ - 30 i bias [] q g f s [] +++ = (1) a v r 9 r 7 ------ - ? ?? ctr () r 11 r 10 --------- ? ?? r 4 r 12 --------- ? ?? 5.1 k w 1k w ------------------ ? ?? 0.07 () 47 k w 1k w ---------------- ? ?? 150 k w 180 k w ------------------- - ? ?? 14 = == v ref r 11 ------------- 4v 47 k w ---------------- - 85 m a ==

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